Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door is wide open for backdoor scrutiny, be it related to RTL, embedded, build, bitstream or any other aspect of design and delivery package. Bujrum!
A eurorack-friendly audio frontend compatible with many FPGA boards, based on the AK4619VN audio CODEC.
Python packages providing a library for Verification Stimulus and Coverage
Functional Coverage and Constrained Randomization Extensions for Cocotb
Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
RTL data structure
A custom AI chip to be taped out soon!
Cosimulation for the Rapid Open Hardware Development (ROHD) framework with other simulators
This repository explores writing cocotb-style tests in modern C++, using coroutines and strong typing, with the goal of maintaining a Python-like test style while potentially improving simulation performance.
micro version of cocotb, to run on microcontrollers or desktop to get hardware in the loop
This site is hopefully a springboard for others to learn about coding in System Verilog and experimenting with FPGAs.
5-Stage Pipelined RISC-V CPU utilizing the RV32I ISA, featuring dynamic branch prediction. Designed, verified, performance tested, and ASIC-flowed
Branch Predictor Optimization for BlackParrot
mirror of https://git.elphel.com/Elphel/vdt-plugin
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