Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
Automatic generation of real number models from analog circuits
An FPGA implementation of Cummings' Asynchronous FIFO
A synthesizable 16-stage pipelined CORDIC engine in Verilog for high-throughput sine and cosine calculation. 🚀
A hardware implementation of component labeling
Parameterized synchronous FIFO buffer implementation in Verilog with pointer-based read/write operations, full/empty flags, and comprehensive testbenches using waveform analysis and gate-level schematic verification. Includes detailed functional verification through simulation testbenches and assertion-based checks to ensure data integrity.
A fully synthesizable SystemVerilog stack and queue for use in larger projects
An Extensible Python Framework for Automated Generation of Synthesizable HDL Code for Finite-State Machines
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