zicsr

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Here are 5 public repositories matching this topic...

rafaelcalcada / rvx

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RISC-V microcontroller for embedded, FPGA and ASIC applications

microcontroller cpu gpio core i2c processor riscv spi uart mcu risc-v rv32i system-on-chip rvx zicsr

Updated Sep 11, 2026
Verilog

LockBlock-dev / Vector

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RISC-V ISA emulator

emulator emulation riscv risc-v rv32i rv32 rv32im risc-v-emulator zicsr

Updated Jan 12, 2025
C++

vohoangnguyennnn / riscv-rv32im-core

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5-stage RV32IM RISC-V CPU and FPGA SoC in SystemVerilog, featuring forwarding, hazard control, machine-mode CSR/traps, precise timer interrupts, TCM, UART, GPIO, and FreeRTOS bring-up.

cpu fpga core rtl freertos systemverilog risc-v coremark tb rv32im 5-stage-pipeline zicsr

Updated Sep 8, 2026
SystemVerilog

W4ilops / riscv-emu

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64-bit RISC-V emulator in Rust with time-travel debugger topics: rust, riscv, emulator, systems-programming, rv64i

emulator rust cpu low-level system-programming 64-bit rv64i risv-v zicsr

Updated May 16, 2026
Rust

Sun-Yingjie / 5stagebymyself

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Verified five-stage RV32IM + Zicsr SystemVerilog core; frozen v0.6 RTL baseline.

cpu rtl systemverilog computer-architecture risc-v iverilog verilator rv32im zicsr five-stage-pipeline

Updated Aug 2, 2026
SystemVerilog

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